1. Field of the Invention
The present invention relates to an internal voltage generating circuit and, more specifically, to an internal voltage generating circuit that can minimize an increase of active consumption current depending on the size of a transistor for a driver used in an active operation.
2. Discussion of Related Art
Generally, as the level of integration in a dynamic random access memory (DRAM) is increased, a gate length and an oxide thickness of a transistor (for example, a metal oxide semiconductor field effect transistor (MOSFET) are reduced. As an external power supply voltage continues to use a high voltage (for example, 5V), however, a channel electric field becomes higher and reaches a voltage-resistant limit of the oxide film. Accordingly, the reliability of a transistor is degraded. In order to solve this problem, a voltage conversion circuit for lowering a power supply voltage within a chip has been actively adopted beginning 16M DRAM. Furthermore, as power consumption of a complementary metal-oxide-semiconductor (CMOS) circuit is proportional to a square of a voltage, there is an advantage that power consumption may be reduced if a low power supply voltage is used. In particular, if an internal voltage source is set to a static voltage, a stable power supply voltage can be secured even if the external power supply voltage is changed, resulting in stabilizing the operation of a chip.
Generally, variation in a load of peripheral circuits, memory arrays, etc., which receive an internal voltage (VINT), is very severe within a DRAM. It is thus difficult to design a circuit having a stabilized operation. For example, an internal voltage (VINT) that is used in a DRAM core, i.e., on the side of a cell and a sub word line driver, a sense amplifier, a X-decoder and a Y-decoder includes a core voltage (VCORE) and a high voltage (VPP) being an electrostatic potential voltage. For instance, if the external power supply voltage (VDD) becomes 2.5V, a core voltage (VCORE) becomes 1.8V. If the external power supply voltage (VDD) is 2.5V, the high voltage (VPP) becomes 3.5V to 3.9V. In an active operation of a DRAM, the core voltage (VCORE) is used. A large amount of current is consumed accordingly. Therefore, the core voltage (VCORE) is generated by an internal voltage generating circuit using an operational amplifier.
FIG. 1 is a circuit diagram illustrating the configuration of a conventional internal voltage generating circuit;
Referring to FIG. 1, a conventional internal voltage generating circuit receives a reference voltage (VREFC) of about 1.8V to output a core voltage (VCORE) of 1.8V. In general, the internal voltage generating circuit consists of an operational amplifier 16, an output driver 14 and an n-channel MOSFET 18 (hereinafter, referred to as ‘NMOS transistor’). The operational amplifier 16 has a non-inverse input terminal (+) to which a reference voltage (VREFC) is inputted and an inverse input terminal (−) to which an output voltage (VCORE) is inputted, and provides the output signal to a gate electrode of a p-channel MOSFET (hereinafter, referred to as ‘PMOS transistor’) of the output driver 14. The output driver 14 has a source electrode to which an external power supply voltage (VDD) is inputted and a drain electrode connected to an output terminal 20. The NMOS transistor 18 is operated by a control voltage (VCON; 0.8V), so that the potential of the output terminal 20 becomes a ground voltage (VSS). As a result, a core voltage (VCORE) that is dropped from the external power supply voltage (VDD) is outputted from the NMOS transistor 18.
This internal voltage generating circuit further includes a PMOS transistor 12 having a gate electrode to which an active signal (act) is inputted so that the driver operates only in an active operation. The PMOS transistor 12 has a source electrode to which the external power supply voltage (VDD) is inputted, and a drain electrode connected to the drive node 19. The PMOS transistor 12 is operated by the active signal (act). If the active signal (act) that is activated in an active operation is inputted as a Low state, the PMOS transistor 12 is turned on and the drive node 19 becomes a High state due to the external power supply voltage (VDD). The output driver 14 is thus turned off. Meanwhile, if the active signal (act) is shifted from a Low state to a High state, that is, when the DRAM is in an active operation, the output driver 14 is turned on.
The size of the output driver 14 is largely related to deviation in the core voltage (VCORE) outputted to the output terminal 20. In other words, according to the speed of current flowing into the output driver 14, a level of the core voltage (VCORE) is changed. For this reason, the size of the output driver 14 can be set by exactly predicting consumption current and loading capacitance of the core voltage (VCORE) that are obtained through simulations. Generally, the size of the PMOS transistor of the output driver 14 is set about 2 to 3 times higher than the results of simulations. There is a limit in increasing the size of the PMOS transistor of the output driver 14 due to several reasons. For this reason, the output driver 14 is usually constructed in several stages using a plurality of PMOS transistors as an option.
As described above, there is a limit in increasing the size of the output driver 14. For example, a level of the core voltage (VCORE) drops by current consumed in an active operation. After a given delay by a response speed of the internal voltage generating circuit, the PMOS transistor of the output driver 14 is operated. Thereafter, the level of the core voltage (VCORE) that drops by the operation of the PMOS transistor of the output driver 14 is forcibly boosted. At this time, if the size of the PMOS transistor of the output driver is large, it is over-damped higher than the core voltage (VCORE) level. Thus, lots of time is consumed until the voltage of the PMOS transistor is restored to an original core voltage (VCORE) level. Furthermore, if the size of the PMOS transistor of the output driver 14 is increased, a layout area of a circuit is also increased.